TSMC 3 nm To Enter Volume Production in 2022 | TechPowerUp

https://www.techpowerup.com/288799/tsmc-3-nm-to-enter-volume-production-in-2022

TSMC will commercialize its N3 (3 nm) EUV silicon fabrication node in 2022, with volume production set to commence in the second half of the year. The company is looking to maximize capacity on its current N5 (5 nm) node, which already serves major customers such as Apple. AMD is expected to utilize N5 allocation going into 2022 as its next-generation "Zen 4" processors are expected to leverage the node to drive up CPU core counts and caches. The company is also utilizing N6 (6 nm) for its CDNA2 compute accelerator logic dies. N5 could also power mobile application processors from several manufacturers.

Samsung’s 10nm and 7nm nodes were both on par with TSMC’s, at least in terms of transistor density, packing 0.52 and 0.95 million transistors per square mm. Meanwhile, Intel’s 10nm node was denser than both, with a density of 1.06 million per square mm. Starting with the 5nm node, Samsung’s nodes have fallen behind. The Korean foundry’s 5nm node has a transistor density of 1.27 million (per mm2), compared to 1.73 million on TSMC’s 5nm and 1.8 million on Intel’s 7nm.

The deltas become even wider with the 3nm node, with Samsung expected to offer a density of just 1.7 million, compared to 2.9 million on TSMC’s 3nm (despite not using GAA), and 3 million on Intel’s 3nm.

The density is actually 100 times as much. Look at the graph, which is properly annotated ("Unit : 100million/square mm").

Still, at 100 MTr/mm², an average transistor measures around 100 nm x 100 nm, so the finest structures, and spacing between them, are probably 15-20 nm wide.

To TSMC's credit, they prefer to talk about node names, like N3 and N4, and avoid mentioning nanometers. Likewise for Samsung (7LPP and such) and lately Intel.