Micro y nanoelectrónica

https://www.hardwaretimes.com/samsungs-3nm-node-expected-to-be-less-denser-than-intels-7nm-and-tsmcs-5nm/ The smaller transistors get, the more expensive they get, and similarly, the harder it becomes for foundries to compete at the cutting edge. We’ve been seeing this since the introduction of TSMC and Samsung’s 7nm node (comparable to Intel’s 10nm process). Global Foundries was the first to drop out of the race, and Intel has been stuck on its 14nm node for nearly seven years (although the chipmaker is trying to make a comeback). Samsung is the third major foundry struggling to keep up with TSMC in the race to make the smallest transistors. Samsung’s 10nm and 7nm nodes were both on par with TSMC’s, at least in terms of transistor density, packing 0.52 and 0.95 million transistors per square mm. Meanwhile, Intel’s 10nm node was denser than both, with a density of 1.06 million per square mm.  Starting with the 5nm node, Samsung’s nodes have fallen behind.  The Korean foundry’s...

https://www.techpowerup.com/288799/tsmc-3-nm-to-enter-volume-production-in-2022 TSMC will commercialize its N3 (3 nm) EUV silicon fabrication node in 2022, with volume production set to commence in the second half of the year. The company is looking to maximize capacity on its current N5 (5 nm) node, which already serves major customers such as Apple. AMD is expected to utilize N5 allocation going into 2022 as its next-generation "Zen 4" processors are expected to leverage the node to drive up CPU core counts and caches. The company is also utilizing N6 (6 nm) for its CDNA2 compute accelerator logic dies. N5 could also power mobile application processors from several manufacturers. Samsung’s 10nm and 7nm nodes were both on par with TSMC’s, at least in terms of transistor density, packing 0.52 and 0.95 million transistors per square mm. Meanwhile, Intel’s 10nm node was denser than both, with a density of 1.06 million per square mm.  Starting with the 5nm node, Samsung’s nodes ...

https://www.adslzone.net/2016/06/27/asi-evolucionado-los-tamanos-fabricacion-semiconductores/

Let’s make something clear:  numbers in front of nm mean nothing! This is from wiki about 7nm lithography: Notice how TSMC 7nm transistor gate pitch is identical to Intel’s 10nm! Also there is absolutely nothing in 7nm dimension range. Notice how Intel “old-fashioned” 10nm tech has smallest metal pitch! TSMC 5nm is not much better then Intel 10nm! So, what you mean by 1nm? Manufacturer BS or real dimension? I’m not sure will we ever have 1nm physical dimension transistor using current tech. 3nm manufacturer BS is already very problematic. At those levels (5nm and bellow) quantum effects are very problematic. There is a “way around” and is called GAA - gate all around. GAA will be first used by Samsung, then Intel while TSMC still stays on FinFET. Next step will be nano-sheet and nano-wire GAA transistors. At physical 1nm are enormous problems. Si atoms are 0.2 - 0.3 nm in diameter what means whole transistor will be 3 - 4 atoms what’s impossible cause MOSFET consists of Drain, Sour...

https://www.itjungle.com/2022/01/10/ibm-and-samsung-go-vertical-to-push-transistor-density-on-chips/ January 10, 2022   Timothy Prickett Morgan Big Blue might have sold off its IBM Microelectronics chip fabrication operation to GlobalFoundries many years ago, but that does not mean that the company does not still do a reasonably large amount of fundamental research into chip maker techniques and tricks. Transistor, chip, and packaging research and development is a big portion of the patent portfolio at IBM and continues to be so because Big Blue still has some of the smartest chipheads on the planet working for it because IBM wants to ensure there is a roadmap for future Power and System z processors and because it can make money licensing the technologies it creates to the fabs of the world. Just after we went on holiday break in the middle of December, IBM and Samsung announced that they have been working together on a new chip making technique called Vertical Transport Field Eff...

https://hardzone.es/noticias/procesadores/tsmc-problemas-3-nm/ Publicado el 22 de febrero, 2022 Era octubre de 2020, ha llovido desde entonces como se suele decir, y en aquel momento lanzamos un artículo que era prácticamente una premonición de lo que vamos a comentar en este:  TSMC tiene problemas con sus 3 nm . Por lo tanto y tomando como base aquel artículo lo que vamos a hacer realmente es actualizar la situación que ya adelantamos en su momento, porque las cosas no pintan nada bien para los taiwaneses. Tres gigantes del sector están pendientes de lo que hace TSMC. Nada menos que AMD, NVIDIA y Apple están con el arco tensado esperando a lanzar la flecha sobre la producción del titán de Taiwán y curiosamente esto puede que sea uno de los problemas que ha encontrado la empresa para cumplir. Se dijo en su momento que los 3 nm o comercialmente hablando su N3 estarían en producción en masa para el 2H de 2023, pero… Uno de los puntos clave de este nodo es que será el último que integ...

https://elchapuzasinformatico.com/2022/02/intel-estudia-la-posibilidad-de-construir-una-fabrica-de-semiconductores-en-la-india/ 21/02/2022 Intel  está que no para, y es que después de anunciar  la adquisición de Tower Semiconductor   por 5.400 millones , adquiriendo así de golpe  nada menos que siete fábricas de producción de semiconductores  situadas en tres países, ahora los rumores de la industria indican que el próximo movimiento de la compañía pasa por  construir una nueva fábrica en la India   aprovechando las subvenciones del gobierno . Curiosamente, es ahora cuando se ha dado a conocer que  Tower Semiconductor ha estado en conversaciones con el gobierno indio durante más de una década , pero aparentemente las dos partes no han podido llegar a un acuerdo adecuado. Ahora es la propia Intel la que se habría metido de por medio en las conversaciones y se está encargando  de que ahora sí se llegue a un acuerdo , y claro, que este acuerdo s...